With the vast and increasing numbers of functions to be performed by mobile devices comes an increased emphasis on battery life. In addition to increasing the ability of a battery to produce and maintain a sustainable long life, there is also an increasing interest into the ability of a mobile device to reduce requirements for total current consumption, not only during actual operation of the mobile device but also during quiescent states. A mobile device should be able to react to a call, a message, or other incoming communication in rapid order. This quick reaction ability conventionally involves the mobile device to preserve the processor state and the contents of high speed random access memory during the “sleep” phase of a mobile device, hence utilizing a “sleep current”.
An example of the current utilization of a conventional mobile device during a quiescent state is shown in FIG. 1. When the mobile device is in the standby state, it may be in a sleep phase 110 for multiples of some period. For example, in a CDMA system the sleep phase may be for multiples of 1.28 seconds. Each paging channel monitoring phase lasts approximately 30 ms. As seen in the FIG. 1, even during the sleep phase 110 there may be an approximately 11 mA current draw, and during a wakeup phase 120 (e.g., during the Quick Page Channel (QPCH) decode) there may be a current draw of approximately 86 mA. As a result the average total current required from the battery during the sleep phase 110 and QPCH decode is approximately 2 mA ([(2.56−0.30)×1/2.56]+(0.30×86)/2.56=2 mA). As can be seen, for the illustrated typical operation, approximately one half of the total current utilization during standby is due to the sleep current of 1 mA. This current may typically be used in conventional architectures in order to preserve the state of volatile memory/internal registers.
FIG. 2 represents a conventional mobile device memory partitioning scheme wherein the power may be controlled by a Power Management Integrated Circuit (PMIC) 10. Power can be supplied to the mobile device processor (MDP) 12, the Flash memory 16 and the Synchronous Dynamic Random Access Memory (SDRAM) 14 during the “active” operation of the mobile device, such as, for example, calling and responding to an incoming call. The MDP 12 may include logic for mobile device operation and analog interfaces, and can further include one or more microprocessors and/or Digital Signal Processors (DSPs). The SDRAM 14 unit may be a volatile memory. The MDP 12 and the SDRAM may use the aforementioned 1 mA power during the sleep phase to preserve their state.
SDRAM such as shown in FIG. 2 is a subset of Random Access Memories (RAMs) in general. RAM can be stand alone devices and/or can be integrated or embedded within devices that use the RAM, such as microprocessors, microcontrollers, application specific integrated circuits (ASICs), system-on-chip (SoC), and other like devices. RAM can be volatile or non-volatile. Volatile RAM loses its stored information whenever power is removed. Non-volatile Flash memory can maintain its memory contents even when power is removed from the memory. Although Flash memory has advantages in the ability to maintain its contents without having power applied, it may have slower read/write times than volatile RAM. Moreover, there may be limitations regarding the number of write operations which can be performed on a Flash memory.
Accordingly, given the aforementioned conventional memory technologies, system designers may contend with difficult compromises between mobile device performance and energy efficiency, even during the sleep phase of the mobile device.